Not known Factual Statements About Anti-Tamper Digital Clocks
Not known Factual Statements About Anti-Tamper Digital Clocks
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17. The equipment for detecting clock tampering as defined in assert fifteen, wherein the Assess circuit is brought on by a clock edge at an conclude in the clock Consider time frame.
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One more aspect of the creation might reside in an apparatus for detecting clock tampering, comprising a circuit that provides a monotone signal, a plurality of resettable delay line segments, and an Consider circuit. The circuit gives the monotone signal during a clock Appraise time period linked to a clock. The plurality of resettable hold off line segments delay the monotone signal to generate a respective plurality of delayed monotone indicators.
A further hold off line segment can have N delay components that deliver the utmost delayed monotone sign 230-N. AND gates while in the hold off strains might Each individual Use a reset enter RST to reset the road amongst the hold off things to set the delay line to an initial regarded state.
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8. An apparatus for detecting clock tampering, comprising: implies for delivering a monotone signal during a clock Consider time period related to a clock;
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The reset time period could possibly be previous to the Appraise time period 310. Using the clock CLK to result in the Consider circuit 220 may utilize a clock edge at an conclude from the Appraise time period to trigger the Appraise circuit.
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an evaluate circuit, induced by a clock, that utilizes the plurality of delayed monotone alerts to detect a voltage fault.